I am a Ph.D. student at School of Computer and Communication Sciences, EPFL .
I completed my B.Tech. (Bachelor of Technology) + M.S. (Master of Science) by research in Electronics and Communications Engineering at International Institute of Information Technology, Hyderabad through a dual degree progamme. I worked with Prof. Suresh Purini for my Master's thesis; we designed an FPGA based hardware accelerator for stereo vision running 1.6 times faster than the state-of-the-art stereo vision implementations on FPGA in 2020.
You can find my resume here.
Besides academia, I am an ardent cricket fan and a skilled player. I am interested in theories of human origin and behavioral studies of humans from the perspective of psychology.
S. Shrivastava, Z. Choudhury, S. Khandelwal and S. Purini, "FPGA Accelerator for Stereo Vision using Semi-Global Matching through Dependency Relaxation,” 2020 30th International Conference on Field-Programmable Logic and Applications (FPL), Gothenburg, Sweden, 2020, pp. 304-309.
S. Khandelwal, Z. Choudhury, S. Shrivastava and S. Purini, "Accelerating Local Laplacian Filters on FPGAs,” 2020 30th International Conference on Field-Programmable Logic and Applications (FPL), Gothenburg, Sweden, 2020, pp. 109-114.
Ph.D. in Computer and Communication Sciences
Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland
2021-2026(expected)
B.Tech. in Electronics and Communcations Engineering + M.S. by research
International Institute of Information Technology - Hyderabad (IIIT-H), India
2016 - 2021